Field of the Invention
The present invention relates to a semiconductor integrated circuit device having an input protective circuit and, more particularly, to an improvement in an input protective circuit including a diode.
In order to protect a semiconductor integrated circuit against external electrostatic noises and/or high abnormal voltages applied accidentally thereto, it is usual to connect a diode to an input bonding pad of the semiconductor integrated circuit as an input protective circuit. A plan view of an example of a conventional input protective circuit is shown in FIG. 1A. FIG. 1B is a cross section taken along a line B--B in FIG. 1A.
In FIGS. 1A and 1B, an input bonding pad 2 and an input wiring layer 3, both being made of aluminum, are formed on an insulating film (not shown) covering a P-type semiconductor substrate 1 on which a semiconductor integrated circuit (not shown) is formed. The input wiring layer 3 is elongated to an input contact of the semiconductor integrated circuit provided behind these elements on FIG. 1A or below these elements on FIG. 1B. Further, a reference potential wiring layer 13 made of aluminum is also formed on the semiconductor substrate for supplying a reference potential (for example, ground potential: GND) to various circuit elements. An N.sup.+ -type semiconductor region 44 of high impurity density included in the semiconductor integrated circuit is connected through contact holes 11 to a branching region of the input wiring layer 3, and a P.sup.+ -type semiconductor region 45 of high impurity density is connected through other contact holes 11 to branching regions of the reference potential wiring layer 13. A diode 46 is thus formed by a PN junction 46 between the N.sup.+ -type semiconductor region 44 and the P.sup.+ -type semiconductor region 45. An equivalent circuit of the input protective circuit 40 shown in FIGS. 1A and 1B is shown in FIG. 1C.
Usually, if an excessive electric field is applied to a gate electrode arranged in a location corresponding to an input contact of a semiconductor integrated circuit having no input protective circuit, a gate insulating film which is formed below the gate electrode and is as thin as several tens nm may be broken down, leading to operational failure of the semiconductor integrated circuit. However, when such abnormally high voltage is applied to the input bonding pad 2 through the input protective circuit as shown in FIGS. 1A to 1C, it is clamped by the protective diode 46 so that electric field strength applied to the gate electrode can be reduced and thus break-down of the gate insulating film is prevented.
However, in the conventional input protective circuit of the semiconductor integrated circuit mentioned above, a clamp level or break-down voltage value of the PN junction diode against high abnormal voltage depends upon impurity densities of the N-type and P-type semiconductor regions 44 and 45. The semiconductor regions 44 and 45 are formed simultaneously with the formation of N.sup.+ -type semiconductor regions and P.sup.+ -type semiconductor regions in a semiconductor circuit region, for providing ohmic contacts to wiring layers. That is, the break-down voltage is determined by only a combination of impurity densities of these regions which is selected to form desired ohmic contacts. The impurity density of the N.sup.+ -type semicondutor region 44 as well as the impurity density of the P.sup.+ -type semiconductor region 45 is selected to form ohmic contacts with the input wiring layer 3 and the reference potential wiring layer 13, respectively.
Therefore, there is a limitation in setting clamp level and it may be impossible to set it to a desired high value. Thus, it is impossible to set clamp level at various levels suitable for various semiconductor integrated circuits, resulting in reduced freedom in designing and manufacturing a semiconductor integrated circuit.
As another conventional technique related to such input protective circuit, FIG. 2 shows an example in which elements within a semiconductor integrated circuit to be protected and protective diodes are formed in a common semiconductor region of a semiconductor substrate. Such semiconductor integrated circuit is disclosed in, for example, Japanese Patent No. Sho 60-56310.
In FIG. 2, a semiconductor integrated circuit is constructed in a P-type well 62 which is one of semiconductor regions of a semiconductor substrate 61. That is, both an field effect transistor (FET) 60 to be protected against abnormal high voltage applied to an input bonding pad 2 and a protective diode 66 for protecting the FET 60 are provided in the same well 62. The FET 60 is constituted with an N.sup.+ -type source region 63 connected to a reference voltage wiring layer 13 for providing Vss or GND, an N.sup.+ -type drain region 64 for sending an output signal of the FET 60 to elements of a subsequent stage, a gate insulating film 68 on a channel region between these regions and a gate electrode 69 formed on the gate insulating film and connected to the input bonding pad 2 to receive an input signal. On the other hand, a P.sup.+ -type semiconductor region 67 for forming an ohmic contact to which the reference voltage wiring layer 13 is connected and an N.sup.+ -type semiconductor region 65 for forming the protective diode 66 which is connected to the input bonding pad 2 are formed in the P-type well 62.
In this semiconductor integrated circuit, the N.sup.+ -type semiconductor region 65 is separated from the P.sup.+ type semiconductor region 67 and the protective diode 66 is constituted by a PN junction 66 formed between the P-type well 62 and the N.sup.+ -type semiconductor region 65. Therefore, its clamp level may higher than that of the circuit shown in FIG. 1. However, since impurity density of the P-type well 62 is determined by a characteristics of such as threshold voltage of the FET, break-down voltage, that is, clamp level of the protective diode 66 cannot be set to a desired value arbitrarily.
Break-down voltage of a clamp diode in such conventional protective circuit depends upon only impurity densities of regions constituting the clamp diode and, therefore, it is very difficult to apply it to a case where semiconductor integrated circuits to be protected require various clamp levels.